The present invention relates to microprocessors and more particularly to the performance, in a microprocessor, of an operation to concatenate at least one bit of a first binary word with bits of a second binary word.
The concatenation of bits is an operation frequently used in industrial data processing. In particular, the authentication codes sent out by microprocessor cards such as bankcards are generated by encryption algorithms requiring numerous bit concatenation operations. Now, the standard microprocessors have the drawback of using several clock cycles and several program code bytes (i.e. 8-bit words) to carry out this operation.
For example, with a 6805 type microprocessor, the bit concatenation is done by means of "BRSET" and "BCLR" instructions and requires first of all the one-setting of the bits of a memory zone designed to contain the result of the operation. Then, the value of a first bit to be concatenated is tested and the first bit of the memory zone is set at 0 if the bit to be concatenated is equal to 0. Then, the value of the second bit to be concatenated is tested and the second bit of the memory zone is set at 0 if the second bit to be concatenated is equal to 0, etc. The concatenation of each bit in the memory zone requires five program code bytes (including instructions and addressing of the memory) and the execution time is about ten machine cycles.
In an 8051-type microprocessor, the bit to be concatenated is first of all loaded into a flag, for example the CRY or carry flag. Then, the bit is inserted into the working registers of the microprocessor by shifting the register rightward by means of the instruction "ROR" or by direct insertion by means of the instruction "MOV". Finally, the contents of the working register are loaded into memory. These operations also consume several bytes of code and take several machine cycles.
Ultimately, the prior art microprocessors are slow to execute a program that contains a large number of concatenation operations and, for each concatenation program, they require the writing of several program codes.
There also exist known sophisticated pipeline type microprocessors, namely microprocessors with overlapping of instructions. The advantage of these microprocessors is that they work at high speed. However, these microprocessors have a degree of complexity, space requirement and cost price that makes them unsuitable for integration into chip cards.
In particular, contactless chip cards powered by electromagnetic induction possess low resources in electrical energy and have to be fitted out with a microprocessor that consumes little current while being fast and capable of processing a transaction in a very short period of time of about some microseconds.
There is also the article by Wai Lung Loh, "BEE: a special-purpose machine for hardware description languages", in the journal Microprocessors and Microsystems, Vol. 19, No. 5, June 1995, that describes a hardware circuit emulator programmed by means of a specific VHDL (hardware description language). This article proposes to facilitate the simulation of operations to manipulate bit strings by making a hardware circuit called a BEE (bitstring emulator engine) taking charge of the execution of such operations. However, the BEE circuit is complex and is ill suited to incorporation into a microprocessor designed for chip cards.
Finally, the U.S. Pat. No. 4,023,023 describes a hardware circuit used to make several operations for shifting and concatenating bits from two binary words given at input.